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Ordering number : ENN7253
CMOS IC
LC723481W,723482W,723483W
Low-Voltage ETR-Controller
Overview
The LC723481W, 723482W, and 723483W are lowvoltage electronic tuning radio microcontrollers that include a PLL that operates up to 250 MHz and a 1/4 duty 1/2 bias LCD driver on chip. These ICs include an on-chip DC-DC converter, making it is easy to create the supply voltages required for tuning and allowing cost reductions in end products. These ICs are optimal for use in low-voltage portable audio equipment that includes a radio receiver.
Package Dimensions
unit: mm 3190A-SQFP64
[LC723481W/2W/3W]
0.5 12.0 10.0
48 49
33 32
Function
* Program memory (ROM): -- 2048 x 16 bits (4K bytes) LC723481W -- 3072 x 16 bits (6K bytes) LC723482W -- 4096 x 16 bits (8K bytes) LC723483W * Data memory (RAM): -- 128 x 4 bits LC723481W -- 192 x 4 bits LC723482W -- 256 x 4 bits LC723483W * Cycle time: 40 s (all 1-word instructions) at 75kHz crystal oscillation * Stack: 4 levels (8 levels) LC723481W(LC723482W/3W) * LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive) * Interrupts: One external interrupt Timer interrupts (1, 5, 10, and 50 ms) * A/D converter: Three input channels (5-bit successive approximation conversion) * Input ports: 7 ports (of which 3 can be switched for use as A/D converter inputs) * Output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are opendrain ports)
Continued on next page.
64 1
(0.5) (1.25) (1.5)
17 16
0.18 0.15
1.7max
0.1
10.0 12.0
SANYO: SQFP64
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
N2002RM (OT) No. 7253-1/15
LC723481W/2W/3W
Continued from preceding page.
*
* *
* *
*
* * *
I/O ports: 16 pins (Of these 8 can be switched over to function as LCD ports as a mask options.) PLL: Dead band control is supported. (Four types) Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz Input frequencies: FM band: 10 to 250 MHz AM band: 0.5 to 40 MHz Input sensitivity: FM band: 35 mVrms (50 mVrms at 130 MHz or higher frequency) AM band: 35 mVrms IF counting: Using the HCTR input pin for 0.4 to 12 MHz signals External reset input: During CPU and PLL operations, instruction execution is started from location 0. Built-in power-on reset circuit: The CPU starts execution from location 0 when power is first applied. Halt mode: The controller-operating clock is stopped. Backup mode: The crystal oscillator is stopped. Static power-on function: Backup state is cleared with the PF port
* Beep tone: 1.5625 and 3.125 kHz * Built-in low-pass filter amplifier: This circuit obviates the need for an external amplifier for the PLL circuit and contributes to reduced end product costs. * Built-in DC/DC converter: Cost reduced in tuner-use power supply circuit * Memory retention voltage: 0.9 V at least * VDD voltage -- PLL: 1.8 to 3.6 V -- CPU: 1.4 to 3.6 V -- ADC: 1.6 to 3.6 V * Optional function switches: -- PH0 to PH3/S13 to S16 -- PG0 to PG3/S17 to S20 -- PG0 to PG3 (open-drain output/general-purpose output) -- PH0 to PH3 (open-drain output/general-purpose output) -- FM DC/DC clock (75 kHz or 1/256 times the local FM oscillator frequency) -- AM DC/DC clock (1/2, 1/4, 1/8, or 1/16 times the AM local oscillator frequency) * Package: SQFP-64 (0.5-mm pitch)
Pin Assignment
63 TEST1 62 AOUT 55 HCTR 54 BRES 53 DBR1 52 DBR2 51 DBR3 50 DBR4 58 AMIN 57 FMIN 56 VDD 59 VSS 64 XIN 61 AIN 60 EO 49 TU
XOUT TEST2 PA3 PA2 PA1 PA0 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0 PD3 PD2
1 2 3 4 5 6 7 8 9 10 11
General-purpose I/O, open drain outputs, segment outputs General-purpose I/O General-purpose I/O, open drain outputs, segment outputs General-purpose inputs/ A/D converter inputs General-purpose unbalanced outputs Open drain outputs General-purpose inputs
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32
COM1 COM2 COM3 COM4 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12
12 13
Open drain outputs
14 15 16
Generalpurpose I/O
28
29
30
S15/PH2
17
18
19
20
21
22
23
24
25
26
INT/PD0
PD2
PE1
BEEP/PE0
ADI3/PF2
ADI1/PF1
ADI0/PF0
S20/PG3
S19/PG2
S18/PG1
27
S17/PG0
S16/PH3
S14/PH1
31
S13/PH0
VSS
No. 7253-2/15
LC723481W/2W/3W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Output voltage Symbol VDD max VIN VOUT(1) VOUT(2) IOUT(1) IOUT(2) Output current IOUT(3) IOUT(4) IOUT(5) Allowable power dissipation Operating temperature Storage temperature Pdmax Topr Tstg All input pins AOUT, PE, TU All output pins except VOUT(1) PC, PD, PG, PH, EO PB AOUT, PE, TU S1 to S20 COM1 to COM4 Ta = -20 to +70C Conditions Ratings -0.3 to +4.0 -0.3 to VDD +0.3 -0.3 to +15 -0.3 to VDD + 0.3 0 to 3 0 to 1 0 to 2 300 3 300 -20 to +70 -45 to +125 Unit V V V V mA mA mA A mA mW C C
Allowable Operating Ranges at Ta = -20 to +70C, VDD = 1.8 to 3.6 V
Parameter Symbol VDD(1) Supply voltage VDD(2) VDD(3) VDD(4) VIH(1) Input high-level voltage VIH(2) VIH(3) VIL(1) Input low-level voltage VIL(2) VIL(3) VIN(1) Input amplitude VIN(2) VIN(3) VIN(4) Input voltage range VIN(5) FIN(1) FIN(2) Input frequency FIN(3) FIN(4) FIN(5) FIN(6) Conditions PLL operating voltage Memory retention voltage CPU operating voltage A/D converter operating voltage Input ports other than VIH(2), VIH(3), AMIN, FMIN, HCTR, and XIN BRES port Port PF Input ports other than VIL(2), VIL(3), AMIN, FMIN, HCTR, and XIN BRES port Port PF XIN FMIN, AMIN FMIN HCTR ADIO, ADI1, ADI3 XIN: CI 35 k FMIN: VIN(2), VDD(1) FMIN: VIN(3), VDD(1) AMIN(H): VIN(2), VDD(1) AMIN(L): VIN(2), VDD(1) HCTR: VIN(4), VDD(1) Ratings min 1.8 1.0 1.4 1.6 0.7 VDD 0.8 VDD 0.6 VDD 0 0 0 0.5 0.035 0.05 0.035 0 70 10 130 2 0.5 0.4 75 3.0 3.0 3.6 3.6 VDD VDD VDD 0.3 VDD 0.2 VDD 0.2 VDD 0.6 0.35 0.35 0.35 VDD 80 130 250 40 10 12 V V V V V V Vrms Vrms Vrms Vrms V kHz MHz MHz MHz MHz MHz typ 3.0 max 3.6 V Unit
No. 7253-3/15
LC723481W/2W/3W Electrical Characteristics within the allowable operating ranges
Parameter Symbol IIH(1) IIH(2) Input high-level current IIH(3) IIL(1) IIL(2) Input low-level current IIL(3) Input floating voltage Pull-down resistor values Hysteresis Voltage doubler reference voltage Voltage doubler step-up voltage VIF RPD(1) RPD(2) VH DBR4 DBR1, 2, 3 VOH(1) VOH(2) Output high-level voltage VOH(3) VOH(4) VOH(5) VOH(6) VOL(1) VOL(2) VOL(3) VOL(4) Output low-level voltage VOL(5) VOL(6) VOL(7) VOL(8) Output off leakage current A/D converter error IDD(1) IDD(2) Current drain IDD(3) IDD(4) IOFF(1) IOFF(2) Conditions XIN: VI = VDD = 3.0 V FMIN, AMIN, HCTR: VI = VDD = 3.0 V PA/PF (without pull-down resistors), the PC, PD, PG, PH, ports, and BRES: VI = VDD = 3.0 V XIN: VDD = VSS FMIN, AMIN, HCTR: VI = VDD = VSS PA/PF (without pull-down resistors), the PC, PD, PG, PH, ports, and BRES: VI = VDD = VSS PA/PF (with pull-down resistors) PA/PF (with pull-down resistors), VDD = 3.0 V TEST1, TEST2 BRES Referenced to VDD, C(3) = 0.47 F, Ta = 25C *1 C(1) = 0.47 F C(2) = 0.47 F, without loading, Ta = 25C *1 PB: IO = -1 mA PC, PD, PG, PH, : IO = -1 mA EO: IO = -500 A XOUT: IO = 200 A S1 to S20: IO = -20 A *1 0.1 VDD 1.3 2.7 VDD - 0.7 VDD VDD - 0.3 VDD VDD - 0.3 VDD VDD - 0.3 VDD 2.0 2.0 0.3 VDD 0.7 VDD 0.3 VDD 0.3 VDD 0.3 VDD 1.0 1.0 1.0 0.5 -3 -100 -1/2 5 0.1 1 0.5 +3 +100 +1/2 75 100 10 0.2 VDD 1.5 3.0 1.7 3.3 VDD - 0.3 VDD -3 -8 3 8 Ratings min typ max 3 20 3 -3 -20 -3 0.05 VDD 200 Unit A A A A A A V k k V V V V
V V V V V V V V V V V V V A nA LSB mA mA A A
COM1, COM2, COM3, COM4: IO = -100 A *1 PB: IO = -50 A PC, PD, PG, PH, PE: IO = -1 mA EO: IO = -500 A XOUT: IO = -200 A S1 to S20: IO = -20 A *1 COM1, COM2, COM3, COM4: IO = -100 A *1 PE: IO = 2 mA AOUT (AIN = 1.3 V), TU: IO = 1 mA, VDD = 3 V Ports PB, PC, PD, PG, PH and EO AOUT, PE and port TU ADI0, ADI1, ADI3, VDD(4) VDD(1): FIN(2) 130 MHz, Ta = 25C VDD(2): In HALT mode, Ta = 25C *2 VDD = 3.6 V, with the oscillator stopped, Ta = 25C *3 VDD = 1.8 V, with the oscillator stopped, Ta = 25C *3
Note: The halt mode current is due to the CPU executing 20 instruction steps every 125 ms.
No. 7253-4/15
LC723481W/2W/3W Note: * C(1), C(2), and C(3) must be connected even if an LCD is not used.
0.1 to 1 F C(C1) 0.1 to 1 F 0.1 to 1 F C(C3) C(C2)
DBR1 DBR2 DBR3 DBR4
Notes: *1. The capacitors C(1), C(2), and C(3) must be connected to the DBR pins. *2. Halt mode current measurement circuit
7 pF 75 kHz
XOUT VDD BRESDBR1 XIN
*3. Backup mode current measurement circuit
7 pF 75 kHz 0.1 F 0.1 F 0.1 F
FMIN AMIN HCTR TEST1, 2 XOUT VDD BRES DBR1 XIN DBR2 DBR3 DBR4 VSS AIN
A
A
7pF
DBR2 DBR3 DBR4 VSS PA, PF AIN
0.1 F 0.1 F 0.1 F
7pF
FMIN AMIN HCTR TEST1, 2
With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected.
With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected.
No. 7253-5/15
LC723481W/2W/3W Block Diagram
XIN XOUT FMIN AMIN PLL DATA LATCH VDD VSS TIME BASE COUNT END CONTROL UNIVERSAL COUNTER (20bits) SEG 4 LA 7 LCPA/B 80 LCD PORT DRIVER DIVIDER SYSTEM CLOCK GENERATOR 1/2 1/16, 1/17 PROGRAMMBLE DIVIDER DIVIDER PLL CONTROL S1 1/8 REFERENCE DIVIDER PHASE DETECTOR 75kHz
FM LOCAL 1/256 AM LOCAL 1/2, 1/4, 1/8, 1/16
EO
TU
LCDA/B
HCTR BRES
1/2
*
P-ON RESET TEST1 TEST2 PA0 PA1 PA2 PA3 PB0 PB1 PB2 PB3 PC0 PC1 PC2 PC3 INT/PD0 PD1 PD2 PD3 AIN AOUT
*
S12 RAM ADDRESS 128 x 4bits(LC723481) DECODER 192 x 4bits(LC723482) 256 x 4bits(LC723483) BANK S13/PH3 S14/PH2 S15/PH1 S16/PH0 S17/PG3 S18/PG2 S19/PG1 S20/PG0 DBR1 DBR2 DBR3 DBR4 COM4 COM3 COM2 COM1
BUS DRIVER
DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER DOUBLER CIRCUIT
DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER DATA LATCH / BUS DRIVER
ROM 2k x 16bits(LC723481) 3k x 16bits(LC723482) 4k x 16bits(LC723483)
BUS CONTROL
INSTRUCTION DECODER ADDRESS DECODER 14 ADDRESS COUNTER 14 STACK SKIP JMP CAL RETURN INTERRUPT RESET BANK CF
COMMON DRIVER
BEEP TONE DATA LATCH BUS DRIVER
/
PE0/BEEP MPX PE1
LATCH A ALU LATCH B
JUDGE
MPX TIMER 0 MPX (5bits) DATA LATCH BUS DRIVER DATA BUS
/
PF0/ADI0 PF1/ADI1 PF2/ADI3
No. 7253-6/15
LC723481W/2W/3W Pin Functions
Pin No. Pin I/O Function I/O circuit
64 1
XIN XOUT
I O
75 kHz oscillator connections
63 2
TEST1 TEST2
I I
IC testing. These pins must be connected to ground during normal operation.
--
Input with built-in pull-down resistor 6 5 4 3 PA0 PA1 PA2 PA3 I Special-purpose key return signal input ports designed with a low threshold voltage. When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key presses can be detected. The four pull-down resistors are selected together in a single operation using the IOS instruction (PWn = 2, b1); they cannot be specified individually. Input is disabled in backup mode, and the pull-down resistors are disabled after a reset.
General-purpose CMOS and n-channel open-drain output shared-function ports. The IOS instruction (Pwn = 2) is used for function switching. 10 9 8 7 PB0 PB1 PB2 PB3 O (b0: PB0, b2: PB1, b3: PB2, PB3) (0: general-purpose CMOS, 1: n-channel opendrain) Special-purpose key source signal output ports. Since unbalanced CMOS output transistor circuits are used, diodes to prevent short-circuits when multiple keys are pressed are not required. These ports go to the output high-impedance state in backup mode. These ports go to the output high-impedance state after a reset and remain in that state until an output instruction (OUT, SPB, or RPB) is executed. *: Verify the output impedance conditions carefully if these pins are used for functions other than key source outputs.
Unbalanced CMOS push-pull
CMOS push-pull 14 13 12 11 18 17 16 15 PC0 PC1 PC2 PC3 INT0/PD0 PD1 PD2 PD3 *2 I/O General-purpose I/O ports. PD0 can be used as an external interrupt port. Input or output mode can be set individually using the IOS instruction (Pwn = 4, 5) by the bit . A value of 0 specifies input, and 1 specifies output. These ports go to the input disabled high-impedance state in backup mode. They are set to function as general-purpose input ports after a reset.
General-purpose output and BEEP output (PE0 shared function ports). The BEEP instruction is used to switch the BEEP/PE0 port between the generalpurpose output port and the BEEP output functions. A BEEP instruction with b2 = 0 will set the BEEP/PE0 port to function as a generalpurpose output port. If b2 is set to 1, the instruction will select the BEEP output function. Bits b0 and b1 switch the frequency of the BEEP output. This IC supports two BEEP frequencies. *: When the PE0 port is set to function as the BEEP output, executing an output instruction for PE0 will only change the value of the internal output latch; it will have no effect on the output. Only the PE0 pin can be switched between the generalpurpose output port and BEEP output functions; the PE1 pin is a dedicated generalpurpose output port. In backup mode, these ports go to the high-impedance state. These ports will remain in that state until either an output instruction or a BEEP instruction is executed. Since these ports are open drain ports, a resistor must be inserted between each port and VDD. At reset, they are set to the general-purpose output port function. N-channel open-drain
20 19
BEEP/PE0 PE1
O
Continued on next page.
No. 7253-7/15
LC723481W/2W/3W
Continued from preceding page.
Pin No. Pin I/O Function General-purpose input and A/D converter input shared function ports. The IOS instruction (Pwn = FH) is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched by the bit, with 0 specifying general-purpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data. *: If an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 5-bit successive approximation type converter, and features a conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (1FH) is (62/96) VDD. CMOS push-pull Shared function ports that function either as LCD driver segment outputs or generalpurpose I/O ports. The IOS instruction is used to switch between the segment output and the generalpurpose I/O port functions. * When used as segment output ports The IOS (Pwn=8) instruction is used to set the general-purpose I/O port. b0 to 3 = S17 to S20/PG0 to PG3 (0: Segment output, 1: PG0 to PG3) The IOS (Pwn=9) instruction is used to set the general-purpose I/O port. b0 to 3 = S13 to S16/PH0 to PH3 (0: Segment output, 1: PH0 to PH3) * When used as general-purpose I/O ports The IOS instruction (Pwn=6, 7) is used to switch the I/O direction. The directions of these pins can be set individually in 1-bit units. b0 = PG0 b1 = PG1 b2 = PG2 b3 = PG3 0: Input 1: Output b0 = PH0 b1 = PH1 b2 = PH2 b3 = PH3 0: Input 1: Output I/O circuit CMOS input/analog input
23 22 21
PF0/ADI0 PF1/ADI1 PF2/ADI3 I
25 26 27 28 29 30 31 32
PG3/S20 PG2/S19 PG1/S18 PG0/S17 O PH3/S16 PH2/S15 PH1/S14 PH0/S13 *2
In backup mode, if used as general-purpose I/O ports, they will be in the input disabled high-impedance state. If used as segment outputs, they will be held fixed at the low level. Although the general-purpose port/LCD port setting is a mask option, the setup with the IOS instruction described above is also necessary.
CMOS push-pull LCD driver segment output pins. 33 to 44 A 1/4-duty 1/2-bias drive technique is used. S12 to S1 O The frame frequency is 75 Hz. In backup mode, the outputs are fixed at the low level. After a reset, the outputs are fixed at the low level.
45 46 47 48
COM4 COM3 COM2 COM1 O
LCD driver common output pins. A 1/4-duty 1/2-bias drive technique is used. The frame frequency is 75 Hz. In backup mode, the outputs are fixed at the low level. After a reset, the outputs are fixed at the low level.
50 51 52 53
DBR4 DBR3 DBR2 DBR1 I LCD power supply step-up voltage inputs.
Continued on next page. No. 7253-8/15
LC723481W/2W/3W
Continued from preceding page.
Pin No. Pin I/O System reset input. 54 BRES I In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit. N-channel open-drain Function I/O circuit
Tuning voltage generation circuit outputs. 49 TU O These pins include a n-ch transistor, and a tuning voltage can be generated by connecting external coil, diode, and capacitor components.
Special-purpose universal counter input port * To measure a frequency, set up HCTR frequency measurement mode and the measurement time with a UCS instruction (b3 = 0, b2 = 0) and start the count with a UCC instruction. UCS b3 b2 55 HCTR I 0 0 1 0 1 0 Input pin HCTR -- -- Measurement mode Frequency measurement -- -- UCS b1 b0 0 0 1 1 0 1 0 1 Measurement time 1 ms 4 ms 8 ms 32 ms
CMOS amplifier input
The CNTEND flag is set when the count completes. Since the input circuit functions as an AC amplifier in this mode, the input must be capacitance coupled. This pin goes to the input disabled state in backup mode, halt mode, PLL stop mode, and after a reset. FM VCO (local oscillator) input. This pin is selected with the PLL instruction CW1. CW1 b1, b0 0 0 Bandwidth 10 to 250 MHz CMOS amplifier input
57
FMIN
I
The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1. CW1 b1, b0 58 AMIN I 1 1 0 1 Bandwidth 2 to 40 MHz (SW) 0.5 to 10 MHz (MW, LW)
CMOS amplifier input
The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
Continued on next page.
No. 7253-9/15
LC723481W/2W/3W
Continued from preceding page.
Pin No. Pin I/O Function I/O circuit CMOS push-pull Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output. The pin is set to the high-impedance state when the frequencies match. Output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode.
60
EO
O
61 62
AIN AOUT
O
Connections for the built-in transistor used to form a low-pass filter.
24 59 56 Note 2:
VSS VSS VDD --
Power supply pin.
This pin must be connected to ground. This pin must be connected to ground. This pin must be connected to VDD. --
When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set up output mode with an IOS instruction.
No. 7253-10/15
LC723481W/2W/3W Sample Application for Tuning Voltage Generation Circuit Sample Application for Low-Pass Filter Amplifier
XIN 64
XOUT 1
75k Hz
V DD 56
Mask option EO 1/256 FM T 60
FMIN 57
AMIN 58 1/2 to 1/16 AM T
AIN 63
AOUT 49 RADIO ON TU+B Varactor 62
LC723481 DC-DC converter load = 100 kW (When VDD = 1.8 V) 12 Clock frequency during FM reception (When 75 kHz is selected) Clock frequency range during AM reception
10
8 VT voltage - V
6
220H 180H 150H 100H
4
2
0 1 100 Clock frequency - kHz 1000 10000
No. 7253-11/15
LC723481W/2W/3W LC723481W, 723482W and 723483W Series Instruction Set Terminology ADDR b C DH DL I M N Rn Pn PW r ( ), [ ] M (DH, DL) : Program memory address : Borrow : Carry : Data memory address High (Row address) [2 bits] : Data memory address Low (Column address) [4 bits] : Immediate data [4 bits] : Data memory address : Bit position [4 bits] : Resister number [4 bits] : Port number [4 bits] : Port control word number [4 bits] : General register (One of the addresses from 00H to 0FH of BANK0) : Contents of register or memory : Data memory specified by DH, DL
Instructions
Mnemonic AD ADS
Operand 1st r r r r M M M M r r r r M M M M 2nd M M M M I I I I M M M M I I I I Add M to r
Function
Operations function r (r) + (M) r (r) + (M), skip if carry r (r) + (M) + C r (r) + (M) + C skip if carry M (M) + I M (M) + I, skip if carry M (M) + I + C M (M) + I + C, skip if carry r (r) - (M) r (r) - (M), skip if borrow r (r) - (M) - b r (r) - (M) - b, skip if borrow M (M) - I M (M) - I, skip if borrow M (M) - I - b M (M) - I - b, skip if borrow
Instruction format f 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 e 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 d 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 c 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 a 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 9 8 7 6 5 4 3 2 r r r r I I I I r r r r I I I I 1 0
DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH
DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL
Add M to r, then skip if carry Add M to r with carry Add M to r with carry, then skip if carry Add I to M Add I to M, then skip if carry Add I to M with carry Add I to M with carry, then skip if carry Subtract M from r Subtract M from r, then skip if borrow Subtract M from r with borrow Subtract M from r with borrow, then skip if borrow Subtract I from M Subtract I from M, then skip if borrow Subtract I from M with borrow Subtract I from M with borrow, then skip if borrow
Addition instructions
AC ACS AI AIS AIC AICS SU SUS
Subtraction instructions
SB SBS SI SIS SIB SIBS
Continued on next page.
No. 7253-12/15
LC723481W/2W/3W
Continued from preceding page.
Instructions
Mnemonic SEQ SEQI SNEI SGE SGEI SLEI AND
Operand 1st r M M r M M r M r M r M r r M r M M1 M M M M r M r M2 I N N 2nd M I I M I I M I M I M I
Function Skip if r equal to M Skip if M equal to I Skip if M not equal to I Skip if r is greater than or equal to M Skip if M is greater than equal to I Skip if M is less than I AND M with r AND I with M OR M with r OR I with M Exclusive OR M with r Exclusive OR M with M Shift r right with carry Load M to r Store r to M Move M to destination M referring to r in the same row Move source M referring to r to M in the same row Move M to M in the same row Move I to M Test M bits, then skip if all bits specified are true Test M bits, then skip if all bits specified are false Jump to the address Call subroutine Return from subroutine Return from interrupt
Operations function (r) - (M), skip if zero (M) - I, skip if zero (M) - I, skip if not zero (r) - (M), skip if not borrow (M) - I, skip if not borrow (M) - I, skip if borrow r (r) AND (M) M (M) AND I r (r) OR (M) M (M) OR I r (r) XOR (M) M (M) XOR I carry (r) r (M) M (r) [DH, Rn] (M) M [DH, Rn] [DH, DL1] [DH, DL2] MI
Instruction format f 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 e 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 d 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 c 1 1 0 1 1 0 0 0 0 0 1 1 0 1 1 1 1 0 0 1 1 b 0 1 0 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 a 0 0 1 0 1 1 0 1 0 1 0 0 0 0 1 0 1 0 1 0 1 9 8 7 6 5 4 3 2 r I I r I I r I r I r I 0 r r r r r DL2 I N N 1 0
Comparison instructions
DH DH DH DH DH DH DH DH DH DH DH DH 0 0 1
DL DL DL DL DL DL DL DL DL DL DL DL 1 1
Logic instructions
ANDI OR ORI EXL EXLI SHR LD
DH DH DH DH DH DH DH DH
DL DL DL DL DL1 DL DL DL
Transfer instructions
ST MVRD MVRS MVSR MVI
Jump and subroutine Bit test call instructions instructions
TMT TMF JMP CAL RT RTI
if M (N) = all 1s, then skip 1 if M (N) = all 0s, then skip 1 PC ADDR PC ADDR Stack (PC) + 1 PC Stack PC Stack, BANK Stack, CARRY Stack 1 1 0 0
ADDR ADDR
ADDR (13 bits) ADDR (13 bits) 0 0 1 1 0 0 0 0 0 1
Continued on next page.
No. 7253-13/15
LC723481W/2W/3W
Continued from preceding page.
Instructions
Mnemonic SS
Operand 1st SWR SWR SRR SRR N M I I I I I PWn M M M P1n P1n P1n P1n N Pn Pn Pn N N N N 2nd N N N N
Function Set status register Reset status register Test status register true Test status register false Test Unlock F/F Load M to PLL register Set I to UCCW1 Set I to UCCW2 Beep control Dead zone control Set timer register Set port control word Input port data to M Output contents of M to port Input port data to M Set port1 bits Reset port1 bits
Operations function (Status W-reg) N 1 (Status W-reg) N 0 if (Status R-reg) N = all if (Status R-reg) N = all if Unlock F/F (N) = all 0s, then skip PLL reg PLL data UCCW1 I UCCW2 I BEEP reg I DZC reg I Timer reg I IOS reg PWn N M (Pn) P1n M M (Pn) (Pn)N 1 (Pn)N 0
Instruction format f 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 e 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 1 1 d 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 c 1 1 1 1 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1 b 1 1 1 1 0 1 0 0 0 0 0 1 1 1 1 0 0 1 1 a 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 1 9 1 1 0 0 0 8 1 1 0 0 0 DH 0 0 0 0 0 0 0 0 0 1 1 7 0 0 0 1 1 1 6 5 4 3 2 N N N N 1 N r 1 0 0 1 0 I I I I I N Pn Pn Pn N N N N 1 0 0 SWR 1 SWR SRR SRR 0
Status register instructions
RS TST TSF TUL PLL
DL 0 0 1 0 1 0 1 1 1 0
Hardware control instructions
UCS UCC BEEP DZC TMS IOS IN OUT
PWn DL DL DL Pn Pn Pn Pn
DH DH DH 1 1 0 0 0 1 0 1
I/O instructions
INR SPB RPB TPT TPF
Test port1 bits, then skip if all bits if (Pn)N = all 1s, then skip 1 specified are true Test port1 bits, then skip if all bits if (Pn)N = all 0s, then skip 1 specified are false BANK I 0
Bank switching instructions
BANK
I
Select Bank
0
0
0
0
0
0
0
0
1
1
1
I
LCD instructions
LCDA LCDB LCPA LCPB HALT CKSTP NOP
M M M M I
I I I I
Output segment pattern to LCD digit direct Output segment pattern to LCD digit through LA Halt mode control Clock stop No operation
LCD (DIGIT) M LCD (DIGIT) LA M HALT reg I, then CPU clock stop Stop x'tal OSC No operation
1 1 1 1 0 0 0
1 1 1 1 0 0 0
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 1 0 0 0
DH DH DH DH 0 0 0 0 0 0 0 0 0
DL DL DL DL 1 1 0 0 0 0 0 1 0
DIGIT DIGIT DIGIT DIGIT I
Other instructions
No. 7253-14/15
LC723481W/2W/3W
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of November, 2002. Specifications and information herein are subject to change without notice. PS No. 7253-15/15

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